Advanced Semiconductor Packaging 2024-2034: Forecasts, Technologies, Applications: IDTechEx

1. EXECUTIVE SUMMARY 1.1. Advanced semiconductor packaging technologies – our scope 1.2. Semiconductor foundries and their roadmap 1.3. Challenges in transistor scaling 1.4. Chiplets: Use cases and benefits 1.5. Four key drivers for advanced semiconductor packaging technologies 1.6. Key markets for advanced semiconductor packaging 1.7. Evolution roadmap of semiconductor packaging 1.8. Moving towards 3D packaging: Pros and Cons 1.9. Four key factors of advanced semiconductor packaging 1.10. Overview of interconnection technique in semiconductor packaging 1.11. Overview of 2.5D packaging structure 1.12. Tech development trend for 2.5D packaging 1.13. Benchmark of materials for interposer 1.14. Interposer supplier landscape 1.15. Advanced Semiconductor packaging – technology benchmark overview (1) 1.16. Advanced Semiconductor packaging – technology benchmark overview (2) 1.17. Evolution of bumping technologies 1.18. Bumpless Cu-Cu hybrid bonding 1.19. Overview of devices that make use of hybrid bonding 1.20. Challenges in 3D Hybrid bonding 1.21. Key applications of 3D SoIC packages 1.22. The emergence of co-packaged optics (CPO) 1.23. Co-packaged optics – package structure 1.24. Future applications of Monolithic 3D 1.25. Data center accelerator: advanced semiconductor packaging unit forecast 2022-2034 (shipment) 1.26. Data center CPU: advanced semiconductor packaging unit forecast 2022-2034 (shipment) 1.27. Advanced semiconductor packaging unit forecast for APE (application processor environment) in consumer electronics 2022-2034 (1) 1.28. Advanced semiconductor packaging units in PC forecast 2022-2034 (1) 1.29. Advanced semiconductor packaging unit for 5G RAN networks 2022-2034 (Cumulative) 2. INTRODUCTION TO ADVANCED SEMICONDUCTOR PACKAGING 2.1. Challenges in transistor scaling 2.1.1. The growing demand for data computing power 2.1.2. Fundamentals of abundant data computing system 2.1.3. Key parameter of growth for processor and memory (1) 2.1.4. Key parameter of growth for processor and memory (2) 2.1.5. Memory bandwidth deficit 2.1.6. Four key area of growth for abundance data computing system 2.1.7. Key parameters for transistor device scaling 2.1.8. Evolution of transistor device architectures 2.1.9. Scaling technology roadmap overview 2.1.10. Semiconductor foundries and their roadmap 2.1.11. The economics of scaling 2.1.12. Challenges in transistor scaling 2.1.13. The solution forward: chiplet + advanced semiconductor packaging 2.2. The rise of Chiplet 2.2.1. The rise of chiplets 2.2.2. What is chiplet technology 2.2.3. Use cases and benefits 2.2.4. AMD Chiplet performance vs cost 2.2.5. Advanced semiconductor packaging: The chiplet enabler 2.3. The rise of Advanced Semiconductor Packaging technologies 2.3.1. General electronic packaging – an overview 2.3.2. Advanced semiconductor packaging – an overview 2.3.3. The rise of advanced semiconductor packaging 2.3.4. The challenges of advanced semiconductor packaging and its challenges 2.3.5. Four key drivers for advanced semiconductor packaging technologies 2.3.6. Key figures of merit of advanced semiconductor packaging technologies 3. ADVANCED SEMICONDUCTOR PACKAGING TECHNOLOGIES: DEEP-DIVE INTO 2.5D AND 3D PACKAGING 3.1. Introduction 3.1.1. Four key factors of advanced semiconductor packaging 3.2. Advanced semiconductor packaging technologies – overview of technologies 3.2.1. Evolution roadmap of semiconductor packaging 3.2.2. Semiconductor packaging – an overview of technology 3.2.3. Overview of interconnection technique in semiconductor packaging 3.2.4. Moving towards 3D packaging: Pros and Cons 3.2.5. Interconnection technique – Wire Bond 3.2.6. Interconnection technique – Flip Chip 3.2.7. Interconnection technique – Interposer 3.2.8. Passive vs active interposer 3.2.9. Interconnection technique – technology benchmark 3.3. 2.5D packaging 3.3.1. 2.5D packaging – introduction 3.3.2. 2.5D Packaging – benefits and challenges 3.3.3. Overview 2.5D semiconductor packaging technology 3.4. 2.5D Si-based packaging 3.4.1. 2.5D packaging that involves Si as interconnect 3.4.2. Interposer Structure 3.4.3. Through Si Via (TSV) – now and the future 3.4.4. Through-Si-Via (TSV) fabrication process flow 3.4.5. Through-Si-Via (TSV) fabrication method 3.4.6. SiO2 RDL fabrication 3.4.7. RDL layer thickness 3.4.8. 2.5D Si interposer: Complete process overview 3.4.9. Si Bridge 3.4.10. Si interposer vs Si bridge benchmark 3.4.11. Case studies 3.4.12. Players that have 2.5D Si-based packaging solutions 3.4.13. Developing trend for 2.5D Si-based packaging 3.4.14. Packaging challenges in 2.5D 3.5. 2.5D Organic-based packaging 3.5.1. 2.5D packaging – high density fan-out packaging 3.5.2. Key trends in fan-out packaging 3.5.3. Fan-out packaging process overview 3.5.4. Fan-out chip-first process flow 3.5.5. Fan-out chip-last process flow 3.5.6. Fan-out chip-last RDL formation – development trend 3.5.7. Challenges in future fan-out process 3.5.8. Limitations in organic substrate 3.5.9. Organic RDL 3.5.10. Key Factors to Consider When Choosing material for Electronic Interconnects 3.5.11. Electronic interconnects: SiO2 vs Organic dielectric 3.5.12. Key parameters for organic RDL materials for next generation 2.5D fan-out packaging 3.6. 2.5D glass-based packaging 3.6.1. Benefits of glass 3.6.2. Roles of glass in semiconductor packaging 3.6.3. Value proposition of glass as core material for 2.5D package 3.6.4. Overcoming Limitations of Si interposers with Glass 3.6.5. Glass core as interposer for advanced semiconductor packaging 3.6.6. Glass core (interposer) package – process flow 3.6.7. TGV – Player and products benchmark 3.6.8. TGV of >15 aspect ratio 3.6.9. Samtec TGV 3.6.10. Absolic’s glass packaging solution 3.6.11. Achieving 2/2 um L/S on glass substrate 3.6.12. Eight metal layer RDL on glass process flow 3.6.13. <3 um micro via 3.6.14. 3D Glass Panel Embedding (GPE) package 3.6.15. 3D Glass Panel Embedding (GPE) package- process flow 3.6.16. Glass vs molding compound 3.6.17. GPE vs Glass interposer – 1 3.6.18. GPE vs Glass interposer – specification benchmark 3.6.19. GPE vs Glass interposer – process benchmark 3.6.20. Glass – thermal management 3.6.21. RDL dielectrics on glass substrate 3.6.22. Glass interposer – more demonstrated case studies 3.6.23. Challenges of glass packaging 3.7. Technology Benchmark: Si vs Organic vs Glass 3.7.1. Benchmark of materials for interposer 3.7.2. Interposer supplier landscape 3.7.3. Advanced Semiconductor packaging – technology benchmark overview (1) 3.7.4. Advanced Semiconductor packaging – technology benchmark overview (2) 3.8. 3D Hybrid bonding 3.8.1. Conventional 3D packaging (No TSVs) 3.8.2. Advanced 3D Packaging (W/ TSVs) 3.8.3. Advanced 3D Packaging 3.8.4. Evolution of bumping technologies 3.8.5. µ bump for advanced semiconductor packaging 3.8.6. Challenges in scaling bumps 3.8.7. Bumpless Cu-Cu hybrid bonding 3.8.8. Cu-Cu hybrid bonding manufacturing process flow 3.8.9. Three ways of Cu-Cu hybrid bonding 3.8.10. Technology benchmark between 2.5D, 3D micro bump, and 3D hybrid bonding 3.8.11. Performance benchmark of devices based on micro bumps vs Cu-Cu bumpless hybrid bonding 3.8.12. Overview of devices that make use of hybrid bonding 3.8.13. Challenges in 3D Hybrid bonding 4. ADVANCED SEMICONDUCTOR PACKAGING TECHNOLOGIES: PLAYER ANALYSIS 4.1. Introduction 4.1.1. Business value chain in IC industry 4.1.2. Ecosystem/Business model in the IC industry 4.1.3. Role and advantages of players in advanced semiconductor packaging market 4.1.4. Players in advanced semiconductor packaging and their solutions 4.2. TSMC’s advanced semiconductor packaging solutions 4.2.1. TSMC’s advanced semiconductor packaging technology portfolio 4.2.2. TSMC 2.5D packaging technology – CoWoS 4.2.3. CoWoS – development progress 4.2.4. Challenges in large interposer manufacturing and its solutions 4.2.5. CoWoS-L 4.2.6. CoWoS_L process flow 4.2.7. Fabrication of Local Si Interconnect (LSI) 4.2.8. Solutions to achieve > 4000 mm2 interposer area (1) 4.2.9. Solutions to achieve > 4000 mm2 interposer area (2) 4.2.10. Test vehicle results 4.2.11. TSMC CoWoS market 4.2.12. TSMC packaging facility overview 4.2.13. TSMC 2.5D packaging technology – InFO 4.2.14. TSMC 2.5D InFO packaging technologies roadmap 4.2.15. TSMC 2.5D packaging technology applications 4.2.16. TSMC 3D SoIC Technology 4.2.17. Roadmap of bond pitch scaling 4.2.18. How bonding pitch size affects system performance 4.2.19. Key Applications of 3D SoIC packages 4.2.20. Application examples of 3D SoIC packages 4.2.21. Combine 3D SoIC and 2.5D backend packaging technologies 4.2.22. TSMC’s vision and strategies for advanced semiconductor packaging 4.3. Intel’s advanced semiconductor packaging solutions 4.3.1. Intel’s advanced semiconductor packaging technology portfolio 4.3.2. Introduction to Intel EMIB (Embedded Multi-Die interconnect Bridge) 4.3.3. EMIB process flow 4.3.4. EMIB process challenges 4.3.5. EMIB key parameters 4.3.6. EMIB bump size reduction roadmap 4.3.7. Products that use EMIB technology 4.3.8. Intel 3D FOVEROS technology 4.3.9. Intel 3D FOVEROS ODI 4.3.10. Intel’s 3D FOVEROS roadmap highlights 4.3.11. Three key interconnect breakthroughs from Intel 4.3.12. Intel 3D FOVEROS Direct hybrid bonding – roadmap 4.3.13. Intel interconnect technology – Zero Misaligned Via (ZMV) 4.3.14. Table of Intel’s products that adopts 3D FOVEROS 4.3.15. Intel Lakefield packaging insights 4.3.16. Intel Lakefield packaging teardown 4.3.17. Intel Ponte Vecchio packaging insights (1) 4.3.18. Intel Ponte Vecchio packaging insights (2) 4.3.19. Intel Ponte Vecchio – thermal management (1) 4.3.20. Intel Ponte Vecchio – thermal management (2) 4.3.21. Intel 3D packaging roadmap: Co-EMIB (2.5D+3D) 4.3.22. Intel advanced packaging roadmap overview 4.3.23. Intel glass packaging roadmap 4.3.24. Intel’s test vehicle for glass packaging 4.3.25. Intel packaging sites 4.4. Samsung’s advanced semiconductor packaging solutions 4.4.1. Samsung’s advanced semiconductor packaging technology portfolio 4.4.2. Overview of Samsung’s targeted applications 4.4.3. Samsung’s advanced semiconductor packaging roadmap 4.4.4. Samsung’s 2.5D packaging solutions (I-Cube) 4.4.5. Samsung RDL-first fan-out wafer/panel level package 4.4.6. 2.5D Molded Interposer on Substrate (MIoS) package 4.4.7. Samsung’s 2.5D packaging solutions (H-Cube) 4.4.8. Fan-out packaging portfolio 4.4.9. FOPLP for HPC products? 4.4.10. Samsung’s 3D packaging solutions 4.4.11. Samsung’s Cu-Cu bonding 4.4.12. Packaging for high bandwidth memory (HBM) 4.4.13. HBM packaging transition to hybrid bonding 4.4.14. Remark on Samsung’s advanced semiconductor packaging business 4.4.15. OSAT’s advanced semiconductor packaging technologies 4.5. ASE’s advanced semiconductor packaging solutions 4.5.1. ASE 2.5D technologies – FOCoS 4.5.2. ASE’s VIPack (Advanced packaging solutions for heterogeneous integration) 4.5.3. FOCOS – Packaging spec benchmark 4.5.4. RDL spec benchmark (FOCOS vs Bridge vs Si interposer) 4.5.5. ASE FOCoS process flow (1) 4.5.6. ASE FOCoS process flow (2) 4.5.7. Pros and Cons of FOCoS chip last 4.5.8. ASE FOCoS chip last package characteristic 4.5.9. SPIL’s advanced semiconductor packaging solutions 4.5.10. SPIL’s advanced packaging solutions 4.5.11. SPIL Fan-Out Embedded Bridge (FOEB) Technology 4.5.12. SPIL FOEB Technology process flow 4.5.13. SPIL FOEB – Thermal and Warpage 4.5.14. SPIL FOEB-T 4.5.15. FO-EB-T Process flow 4.5.16. Performance benchmark: FOEB vs FOEB-T vs 2.5D Si interposer 4.5.17. SPIL FOEB vs Intel EMIB 4.6. Amkor’s advanced semiconductor packaging solutions 4.6.1. Amkor advanced semiconductor packaging solutions 4.6.2. Amkor’s 2.5D TSV FCBGA 4.6.3. Summary of Amkor’s 2.5D TSV technologies 4.6.4. Stacked substrate (2.5D packaging) from Amkor 4.6.5. High-Density Fan-Out (HDFO) solution from Amkor 4.6.6. Amkor’s S-SWIFT packaging solution (1) 4.6.7. Amkor’s S-SWIFT packaging solution (2) 4.6.8. Amkor – RDL layers development 4.6.9. Electrical characteristics vs different RDL solution 4.6.10. Amkor’s S-SWIFT package development status 4.6.11. Amkor – 3D stacking 4.6.12. Amkor – Cu-Cu Hybrid bonding pathfinding on the way 5. ADVANCED SEMICONDUCTOR PACKAGING TECHNOLOGIES: APPLICATIONS 5.1. Introduction 5.1.1. Packaging trend for key markets 5.2. AI 5.2.1. Challenges for next generation AI chips 5.2.2. The rise and the challenges of LLM 5.2.3. Fundamentals of abundance data computing system 5.2.4. State-of-the-art high-end AI chips 5.2.5. Evolution of AI compute system architecture 5.2.6. NVIDIA and AMD solutions for next-gen AI 5.2.7. The next step forward to improve system bandwidth 5.2.8. How advanced semiconductor packaging can address the challenges? 5.2.9. Why traditional Moore’s Law scaling can’t meet the growing needs for HPC 5.2.10. Key Factors Affecting HPC Datacenter Performance 5.2.11. Advanced semiconductor packaging path for HPC 5.2.12. HPC chips integration trend – overview 5.2.13. HPC chips integration trend – explanation 5.2.14. Enhancing Energy Efficiency Through Hybrid Bonding Pitch Scaling 5.2.15. What is critical in packaging for AI&HPC 5.2.16. Case studies 5.2.17. 3D Chiplets stacking using hybrid bonding – Graphcore 5.2.18. AMD’s Vision for Advanced Semiconductor Packaging 5.2.19. 3D chip stacking using hybrid bonding – AMD 5.2.20. 3D Chiplets stacking using hybrid bonding – AMD 5.2.21. AMD Instinct MI300 5.2.22. Addressing Power Consumption Challenges in Expanding Computing System 5.2.23. Silicon photonics 5.2.24. Future system-in-package architecture 5.3. CPUs in data center servers and switches 5.3.1. Intel vs AMD for Server CPUs 5.3.2. Advanced semiconductor packaging for Intel latest Xeon server CPU (1) 5.3.3. Advanced semiconductor packaging for Intel latest Xeon server CPU (2) 5.3.4. AMD chip semiconductor packaging roadmap 5.3.5. Options for Integrating Multiple Chips 5.3.6. AMD’s semiconductor packaging choices for chiplet integration 5.3.7. Future packaging trend for chiplet server CPU 5.3.8. Accelerators in data center servers and switches 5.3.9. Accelerators in servers 5.3.10. Server board layout – with accelerators (1) 5.3.11. Server board layout – with accelerators (2) 5.3.12. GPUs as data center accelerators 5.3.13. Computer memory hierarchy 5.3.14. HBM vs DDR for computing (1) 5.3.15. Drawbacks of High Bandwidth Memory (HBM) 5.3.16. Summary of HBM vs DDR 5.3.17. HBM vs DDR for computing – market trend 5.3.18. HBM (High Bandwidth Memory) packaging 5.3.19. HBM packaging transition to hybrid bonding 5.3.20. Benchmark HBM performance 5.3.21. Approaches to package HBM and GPU 5.3.22. AMD new server GPU featuring new semiconductor packaging approach 5.3.23. AMD Elevated fanout bridge 2.5D 5.3.24. AMD patents GPU chiplet design for future graphics cards 5.3.25. AMD GPU memory choice for different applications 5.3.26. NVIDIA GPU for data centers 5.3.27. Computing modules with HBM (1) 5.3.28. Computing modules with HBM (2) 5.3.29. FPGA as data center accelerators 5.3.30. Server board layout – with FPGA accelerators 5.3.31. Intel FPGA packaging 5.3.32. Xilinx FPGA packaging 5.3.33. High-end commercial chips based on advanced semiconductor packaging technology (1) 5.3.34. High-end commercial chips based on advanced semiconductor packaging technology (2) 5.3.35. Summary 5.4. Co-Packaged Optics 5.4.1. The emergence of co-packaged optics (CPO) 5.4.2. Co-packaged optics for network switch 5.4.3. Pluggable optics vs CPO – 1 5.4.4. Pluggable optics vs CPO – 2 5.4.5. Optical dies integration for compute silicon 5.4.6. Thermal management for compute silicon 5.4.7. Future challenges in CPO 5.4.8. Co-packaging vs Co-packaged optics (CPO) 5.4.9. Co-packaged optics – package structure 5.4.10. Value proposition of CPO 5.4.11. Co-Packaged Optics (CPO), key for advancing switching and AI networks 5.4.12. Key technology building blocks for CPO 5.4.13. Key packaging components for CPO 5.4.14. Broadcom’s CPO development timeline 5.4.15. Broadcom’s CPO portfolio 5.4.16. Fan-Out Embedded Bridge (FOEB) Structure for Co-Packaged Optics 5.4.17. Glass-based Co-packaged optics – vision 5.4.18. Glass-based Co-packaged optics – Packaging structure 5.4.19. Glass-based Co-packaged optics – process development 5.4.20. Corning’s 102.4 Tb/s test vehicle 5.4.21. Turn-Key solution required for CPO 5.5. Automotive 5.5.1. Future ADAS/Autonomous driving systems: requirements, actions, and current challenges 5.5.2. Three transformational pillars in automotive electronics 5.5.3. Autonomous vehicles (AVs) – an overview 5.5.4. The Automation Levels in Detail 5.5.5. Typical Sensor Suite for Autonomous Cars 5.5.6. The Coming Flood of Data in Autonomous Vehicles 5.5.7. High demand for computing power in autonomous vehicles 5.5.8. Semiconductor Content Increase in AVs 5.5.9. Autonomous driving platform – processors and chip packaging 5.5.10. The primary differentiators for AVs will be chip design and software 5.5.11. Autonomous driving platform – processors and packaging roadmap (1) 5.5.12. Autonomous driving platform – processors and packaging roadmap (2) 5.5.13. Chip design and packaging choice for AV computing processers from different suppliers 5.5.14. NVIDIA’s AV computing modules for L5 automotive 5.5.15. Self-driving computing module packaging challenges 5.5.16. Autonomous vertical integration 5.5.17. Autonomous – packaging for sensors 5.5.18. Autonomous – packaging for sensors 5.5.19. Packaging for sensors in ADAS (1) 5.5.20. Packaging for sensors in ADAS (2) 5.5.21. Future Radar Packaging Choices 5.5.22. Radar IC packages 5.6. 5G&Beyond 5.6.1. Introduction to 5G 5.6.2. Mobile Telecommunication Spectrum and Network Deployment Strategy 5.6.3. Summary of Key 6G Activities and Future Roadmap 5.6.4. 5G Commercial/Pre-commercial Services by Frequency (2023) 5.6.5. 5G infrastructure 5.6.6. Different RAN architectures 5.6.7. Samsung’s VRAN solution 5.6.8. Ericsson’s cloud RAN solution 5.6.9. Open RAN deployment based on commercial off-the-shelf (COTS) hardware 5.6.10. Ultra-low latency networks require accelerator card 5.6.11. Open RAN infrastructure arrangement 5.6.12. Software defined radio (SDR) 5.6.13. Massive MIMO (mMIMO) 5.6.14. Block diagram of MIMO antenna array system 5.6.15. Integration of digital frontend with transceivers 5.6.16. Si design for Open RAN radio (Analog Devices case) 5.6.17. Marvell baseband Si for 5G Open RAN radio 5.6.18. Marvell SoC for 5G networks (2) 5.6.19. Xilinx’s Si solution for 5G radio unit (1) 5.6.20. Xilinx’s Si solution for 5G radio unit (2) 5.6.21. End-to-end 5G silicon solutions from intel 5.6.22. Intel’s FPGA for 5G radio (1) 5.6.23. Intel’s FPGA for 5G radio (2) 5.6.24. The intentions of 5G system vendors enter Si battleground 5.6.25. 5G base station types: macro cells and small cells 5.6.26. 5G radios by MIMO size unit forecast 2022-2032 (Cumulative) 5.6.27. Estimating the total addressable market for advanced semiconductor packaging in 5G RAN infrastructure 2022-2032 (Cumulative) 5.6.28. Advanced semiconductor packaging unit for 5G RAN networks 2022-2032 (Cumulative) 5.6.29. 5G mmWave Antenna in Package (AiP) 5.6.30. Packaging trends for 5G and 6G connectivity 5.6.31. High frequency integration and packaging trend 5.6.32. Example: Qualcomm mmWave antenna module 5.6.33. High frequency integration and packaging: Requirements and challenges 5.6.34. Three ways of mmWave antenna integration 5.6.35. Technology benchmark of antenna packaging technologies 5.6.36. AiP development trend 5.6.37. Two types of AiP structures 5.6.38. Two types of IC-embedded technology 5.6.39. Two types of IC-embedded technology 5.6.40. Key market players for IC-embedded technology by technology type 5.6.41. University of Technology, Sydney: AME antennas in packages for 5G wireless devices 5.6.42. Additively manufactured antenna-in-package 5.6.43. Novel antenna-in-package (AiP) for mmWave systems 5.6.44. Design concept of AiP and its benefits (1) 5.6.45. Design concept of AiP and its benefits (2) 5.6.46. Stack-up AiP module on a system board 5.6.47. PCB embedding process for AiP 5.6.48. Section summary and remarks 5.6.49. LTCC AiP for 5G: TDK 5.6.50. Glass substrate AiP for 5G: Georgia Tech 5.6.51. Benchmark of low loss materials for AiP 5.6.52. 5G Aip summary 5.6.53. Phased-array antenna module design trend for 6G generations 5.6.54. 140 GHz Prototype From Samsung and UCSB – IC and Antenna Fabrication Details 5.7. Consumer electronics 5.7.1. Advanced semiconductor packaging technologies for consumer electronics 5.7.2. Commercialized high density fan-out packaging solutions 5.7.3. Samsung’s new galaxy smartwatch 5.7.4. Packaging choices for packaging application processor environment (APE) in consumer electronics (1) 5.7.5. Packaging choices for packaging application processor environment (APE) in consumer electronics (2) 5.7.6. 3D packaging for APE in consumer electronics 5.7.7. Future packaging trend for APE in consumer electronics 5.7.8. Apple’s M1 ultra for workstations uses TSMC’s fan-out technologies 5.7.9. AMD Stacked 3D V-Cache technology for consumer desktop CPU 5.7.10. Intel mobile SoC for laptops (Lakefield) advanced semiconductor packaging 5.7.11. Advanced semiconductor packaging in Intel’s next generation CPU Meteor Lake 6. MONOLITHIC 3D IC 6.1. From 2D system to Monolithic 3D IC (M3D) 6.2. The driving force for Monolithic 3D IC 6.3. 3D Integration technology landscape 6.4. Significantly improved interconnect density with M3D (1) 6.5. Significantly improved interconnect density with M3D (2) 6.6. Heterogenous 3D vs Monolithic 3D 6.7. What are the challenges in making monolithic 3D IC 6.8. 2D Materials for upper layer transistor in Monolithic 3D IC 6.9. CNTs for transistors 6.10. CNFET research breakthrough (1) 6.11. CNFET research breakthrough (2) 6.12. CNFET case study 6.13. Solutions? 6.14. Future applications of M3D 6.15. Future outlook and key takeaway 7. MARKET FORECAST SUMMARY 7.1. Data center server unit forecast 2022-2034 (shipment) 7.2. Total addressable data center CPU market forecast 2022-2034 (Shipment) 7.3. Data center CPU: advanced semiconductor packaging unit forecast 2022-2034 (shipment) 7.4. Total addressable data center accelerator market forecast 2022-2034 (Shipment) 7.5. L4+ Autonomous vehicles sales forecast 2022-2045 7.6. Data center accelerator: advanced semiconductor packaging unit forecast 2022-2034 (shipment) 7.7. Total addressable ADAS processor & accelerator sales market for L4+ autonomous vehicles forecast 2022-2045 7.8. 2.5D advanced semiconductor packaging unit sales for L4+ autonomous vehicles sales forecast 2022-2045 7.9. 3D advanced semiconductor packaging unit sales for L4+ autonomous vehicles forecast 2022-2045 7.10. Advanced semiconductor packaging unit forecast for APE in consumer electronics remarks 7.11. Unit sales forecast for smartphones/tablets/smartwatches/AR/VR/MR 2022-2034 7.12. Advanced semiconductor packaging unit forecast for APE (application processor environment) in consumer electronics 2022-2034 (1) 7.13. Advanced semiconductor packaging unit forecast for APE (application processor environment) in consumer electronics 2022-2034 (2) 7.14. Global PC shipment forecast 2022-2034 7.15. Advanced semiconductor packaging units in PC forecast 2022-2034 (1) 7.16. Advanced semiconductor packaging units in PC forecast 2022-2034 (2) 7.17. 5G radios by MIMO size unit forecast 2022-2034 (Cumulative) 7.18. Estimating the total addressable market for advanced semiconductor packaging in 5G RAN infrastructure 2022-2034 (Cumulative) 7.19. Advanced semiconductor packaging unit for 5G RAN networks 2022-2034 (Cumulative) 8. COMPANY PROFILES

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